Report - Belfer Center for Science and International Affairs, Harvard Kennedy School

Catalyzing Semiconductor Innovation through a National Semiconductor Technology Center

| June 2023

Executive Summary

The National Semiconductor Technology Center (NSTC) is intended to be the central hub for research and engineering within the semiconductor ecosystem. It operates under the Department of Commerce and has the mandate to “advance and enable disruptive innovation to provide U.S. leadership in the industries of the future.” The NSTC along with the National Advanced Packaging Manufacturing Program (NAPMP) has received $11 billion of the total $52 billion allocated in the CHIPS legislation. Recently, the Department of Commerce released a vision and strategy paper outlining three main goals for the NSTC:

1. Extend U.S. leadership in foundational technologies for future applications and industries and strengthen the U.S. semiconductor manufacturing ecosystem.

2. Reduce significantly the time and cost to prototype innovative ideas for member organizations.

3. Build and sustain a semiconductor workforce development ecosystem.

To achieve these objectives, the NSTC will prioritize "lab-to-fab" research, with a focus on a 5 to 15 year time frame. The shared facilities within the NSTC will prioritize flexibility over profitability. Unlike similar centers focused on national security for the Department of Defense (such as the Microelectronics Commons), the NSTC will concentrate on technologies for commercial development and involve various government agencies beyond the Department of Commerce.

The NSTC must develop new and innovative strategies for organizing semiconductor research and development (R&D). The $11 billion allocated to R&D by the CHIPS Act is a drop in the bucket of what many consider to be a required investment for meaningful semiconductor innovation. In this primer, we discuss key implementation strategies for the NSTC to achieve its first two goals (a separate primer on workforce development has been published, see below). We take note of strategic elements which have been raised by the NSTC vision paper, but also find opportunities to delve into the socioeconomic and geopolitical context of the CHIPS legislation, the infrastructure supporting the NSTC, and crucial business considerations for its success. Specifically, we highlight the potential benefits for smaller and medium-sized enterprises, which stand to gain the most from the NSTC.

ORGANIZATION OF THE PRIMER

This primer focuses on the R&D infrastructure authorized by the CHIPS and Science Act, specifically the NSTC. Our main objective is to address the central question: How can the NSTC and the associated semiconductor R&D network catalyze paradigm-shifting innovation and leverage the initial $11 Billion investment for greater returns over several decades?

  • Part 1 provides an overview of the geopolitical and economic context that led to the passage of the CHIPS+ legislation. We emphasize the role of offshoring manufacturing production to Eastern Asia and the strategic chokepoints it has created. A major contributing factor to these chokepoints is the dominance of centralized monopolies in key elements of the manufacturing process, such as Taiwan Semiconductor Manufacturing Company (TSMC) and Samsung in cutting-edge chip production, and ASML with the required tools.
    • We will also discuss several key challenges faced by smaller players in the semiconductor innovation ecosystem. These challenges include the "valley of death," the lack of scale-up funding, and the importance of de-risking investments through competitive guaranteed contracts. 
  • Part 2 focuses on the infrastructure challenges faced by semiconductor innovation, especially from the perspective of smaller- and medium-sized companies (SMEs). We explore the role of different-sized foundries, such as coupon, 200mm, and 300mm, and how the NSTC can leverage existing facilities to distribute the demand for prototyping and scaling up.
  • Part 3 delves into the business structures of government-backed projects, including the role of intellectual property and funding in user facilities. The significant investment made by the industry in R&D results in valuable intellectual property, including patents, trade secrets, source code, and more. SMEs face challenges regarding the protection of their intellectual property and maintaining independence within consortia that consist of much larger companies. Consequently, safeguarding this intellectual property becomes crucial for the industry to maintain its competitive position globally. This section also explores different business models employed in rapid lab-to-fab innovation, such as the NASA Commercial Orbital Transportation Services (COTS) program and Operation Warp Speed. The central objective of these business models is to mitigate risk by providing government-backed loans and guaranteeing customers, whether they are other private entities or the government itself.
For more information on this publication: Belfer Communications Office
For Academic Citation: Drucker, Nathan, Anushka Shah and Ariel Higuchi. “Catalyzing Semiconductor Innovation through a National Semiconductor Technology Center.” Belfer Center for Science and International Affairs, Harvard Kennedy School, June 2023.

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